V0.1.1 ޸ļ¼
1  dma.h  

޸ĺ
extern void DMA_CHx_CR_FTIE_Setable(DMA_CH_Type CHx, FunState NewState);
extern FunState DMA_CHx_CR_FTIE_Getable(DMA_CH_Type CHx);

޸Ķ
DMA_CH2_CR_SSEL_UART0_RX޸ΪDMA_CH2_CR_SSEL_UART0_TX
DMA_CH2_CR_SSEL_UART4_TX޸ΪDMA_CH2_CR_SSEL_UART4_RX

2 spi.c
޸ȥպͷSPIx_TXBUF_TXBUF_MskSPIx_TXBUF_TXBUF_Msk
SPIx_TXBUF_Write(SPI_Type* SPIx, uint32_t SetValue)
SPIx_RXBUF_Read(SPI_Type* SPIx)

3 spi.h
޸λ
SPIx_TXBUF_TXBUF_Msk
SPIx_TXBUF_TXBUF_Msk

4 ֲ޸
 BSTIMжʹܼĴΪBSTIM_IER
 BSTIMGPAT ״̬ĴΪBSTIM_ISR
 صĶ޸ û޸ģ
 
5 GPTIM.h
GPTIMx_CR1_CKDbit޸
 GPTIMx_CR1_CKD_1TCK ΪGPTIMx_CR1_CKD_1TINT

6 ATIM.h
ATIM_CR1_CKDbit޸
ATIM_CR1_CKD_1TINT 

7 ޸startupļж
GPIO_IRQHandler
GPTIM1_IRQHandler
GPTIM0_IRQHandler
LCD_IRQHandler
FLASH_IRQHandler

8 PDR BOR ļĴַ޸

9  RTC_ADJUST_ADJUST_Msk	(0x7ffU << RTC_ADJUST_ADJUST_Pos)޸Ϊ RTC_ADJUST_ADJUST_Msk	(0x1ffU << RTC_ADJUST_ADJUST_Pos)

10 SVDļ

V0.1.2
޸SVDFLMļ
drive  fm33l0xx_dma.cļDMA_CH7_CR_SSEL_Set ޸

V0.1.3
SVD LPUART WKBYTE_CFG 01Ķ巴
޸ fm33l0xx_dma.cfm33l0xx_dma.h  DMA_CHx_CR_BDW_Setable DMA_CHx_CR_BDW_Getable ΪDMA_CHx_CR_BDW_Set DMA_CHx_CR_BDW_Get
޸ fm33l0xx_dma.cfm33l0xx_dma.h  DMA_CHx_CR_CIRC_Set DMA_CHx_CR_CIRC_Get ΪDMA_CHx_CR_CIRC_Setable DMA_CHx_CR_CIRC_Getable
 fm33l0xx_dma.h DMA_CHx_CR_BDW_Mskĺ궨
޸ fm33l0xx_spi.cfm33l0xx_spi.h  SPIx_IER_ERRIE_SetableSPIx_IER_ERRIE_Getable SPIx_IER_TXIE_SetableSPIx_IER_TXIE_Getable SPIx_IER_RXIE_SetableSPIx_IER_RXIE_Getable
m33l0xx.rcc  RCC_PLLDB_WriteEx޸
fm33l0xx.rcc  RCC_GetClocksFreq޸

V0.1.4
1 ޸SVDļ
2 ޸fm33l0xx_rcc.cRCC_GetClocksFreq
3 ޸ģDeinit 
4 ޸fm33l0xx_adc.h  ADC_CHER_AINS_ADC_IN01	(0x1U << ADC_CHER_AINS_Pos)
5 fm33l0xx_atim.hATIM_CCMR2_OCMATIM_CCMR4_OCMĺ궨